Traditional mechatronic systems rely on a centralized CPU connected to a high speed backplane (VME, PCI, etc) in order to sequence and control a complex embedded system. The backplane typically hosts a central CPU and a collection of I/O boards and provides a shared memory interface to access I/O data and communicate with other devices such as drives, and encoders, motors, sensors, etc. While these types of hardware architectures work well for smaller noise-free environments, they tend to be problematic for larger systems where high-speed I/O signals have to travel a long distance. Sending high speed I/O data (analogue or digital) makes a system susceptible to electro-magnetic noise which consequently manifests itself as wrong data, or unscheduled and unexpected interrupts resulting in erroneous system behavior. Such behavior is often sporadic and extremely hard to debug.