In order to significantly speed up verification and to handle complex algorithms that change daily, many companies are turning to a High-Level Synthesis (HLS) methodology. But, it is extremely important that the high-level C++ model is correct. Even if correctly written, the high-level model could be coded in a sub-optimal way, leading to unintended hardware after synthesis. Problems can arise in C++ simulation or lead to simulation mismatches between this simulation and the RTL simulation. Or, a problem could go completely undetected. This white paper explains how to solve all of these issues.