When designers move their untimed C++ design descriptions through a high-level synthesis (HLS) flow, they wonder if the generated, timed RTL is functionally equivalent to the original, high-level description. When they make refinements or optimize RTL for power, they naturally are concerned that these changes no longer meet their original specifications. What designers need is a way to quickly determine design equivalence without the need for testbenches and simulation runs. Download the paper to learn more.