Layout constraints are an essential part of a PCB design. As the technology in modern electronic devices has become more complex (e.g., increasing speed, decreasing rise time and supply voltage values), signal integrity issues have become a primary concern. For many designs, this means a large percentage of nets require PCB layout constraints to meet signal integrity requirements.
This brings two major challenges: creating a proper set of layout constraints for your design and applying those constraints during the PCB layout design process.
This paper shows how PADS helps address the challenges of highly constrained designs.