Ensuring your integrated circuit (IC) design has the ability to withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity in IC circuit design and verification. While automated flows for ESD verification are wellestablished for regular 2D ICs, 2.5D and 3D integration presents new challenges in both ESD design and verification. Although there are some design methodologies to help designers achieve effective ESD protection in 2.5D and 3D ICs, there has been, until now, a distinct lack of automated ESD verification solutions for these technologies. Let’s examine the verification challenges introduced by these integration technologies, and then walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.
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