Keys to Generating 112 PAM-4 SERDES Jitter Requirements

Data communication is constantly evolving, with new technologies being developed to improve the speed and efficiency of data transfer. One of the key challenges of designing with a high-speed SERDES is on clock distribution (analog clock tree). There are many advantages to using ultra-high performance clock synchronizers to generate reference clocks needed for high-speed serial links using 112G PAM-4. This paper describes a methodology for deriving reference clock jitter requirements and outlines the advantages of using the Renesas FemtoClock™ 3 family of low-phase-noise frequency clock synthesizers & jitter attenuators for clocking such a system.

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