To fulfill the performance promise of 5G while ensuring 5G IC designs can be successfully manufactured in commercial quantities, designers of 5G chips and networks need accurate, automated parasitic extraction and simulation of 5G IC layouts so they can reduce the impact of parasitics by optimizing their chips before manufacturing. In 5G design, parasitic extraction EDA tools help engineers validate that their chip designs can handle the high demand of a 5G network and deliver the designed circuit performance by enabling design teams to accurately account for the impact of parasitics on complex components such as FD-SOI transistors and MIM/MOM capacitors, as well as the high frequencies used in these designs.
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