Chip-level physical implementation teams must manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning, blocks placed in the chip-level … [Read more...] about Adopting an Interface DRC Checking Flow
DRC
Color Optimization Considerations in Multi-Patterning
Decomposing multi-patterned design layers into colors has traditionally been an exercise in finding at least one DRC legal coloring solution. In this white paper we discuss how manufacturers at more … [Read more...] about Color Optimization Considerations in Multi-Patterning