As feature sizes decrease there is a growing need for chemical-mechanical polishing (CMP) modeling to better understand how the design layout impacts planarity. CMP modeling has proven to be very … [Read more...] about A Machine Learning Approach to CMP Modeling
Mentor Graphics
Adopting an Interface DRC Checking Flow
Chip-level physical implementation teams must manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning, blocks placed in the chip-level … [Read more...] about Adopting an Interface DRC Checking Flow
Integrating Pattern Matching with DFM Properties to Enhance and Optimize Layouts
In this IC design white paper we explore how the use of pattern matching has expanded into design for manufacturing (DFM) flows and integrates with different types of DFM properties (numeric, strings … [Read more...] about Integrating Pattern Matching with DFM Properties to Enhance and Optimize Layouts
Achieving Optimal Performance During Physical Verification
With increased complexity in design layout requirements at each new node, the compute burden placed on physical verification has grown exponentially. At the same time, designers are generally faced … [Read more...] about Achieving Optimal Performance During Physical Verification
Color Optimization Considerations in Multi-Patterning
Decomposing multi-patterned design layers into colors has traditionally been an exercise in finding at least one DRC legal coloring solution. In this white paper we discuss how manufacturers at more … [Read more...] about Color Optimization Considerations in Multi-Patterning