This 35 minutes presentation highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the Analog FastSPICE Platform.
What you will learn about:
· SERDES design and verification challenges
· Complexity of circuit verification at advanced processes
· Best practices for silicon success using AFS Platform
· Presenter name: Jeff Galloway, Vice President and Co-Founder of Silicon Creations