Artificial intelligence (AI) and machine learning (ML) are seeing growing adoption in a wide range of applications, due primarily to the improvement in algorithms, advancements in hardware design, and the increase in data volume created by digitization of information [1]. The integrated circuits … [Read more...]
Parasitic Extraction of MIM/MOM Capacitor Devices in Analog/RF Designs
Major advances in communications technology offer new opportunities and challenges for radio frequency (RF) design. 5G, the fifth generation of cellular technology, promises to deliver increased speed and improved flexibility of wireless services while reducing latency. The Internet of Things (IOT), … [Read more...]
Improving Productivity With More Efficient LVS Debug
Layout vs. schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SOC) design cycle, but with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a … [Read more...]
Fusing CMOS IC and MEMS Design for IoT Edge Devices
A new breed of designers are creating IoT edge devices that span across analog, digital, RF, and MEMS domains. They are tackling a challenge that once seemed impossible: combining the electronics of the device using the traditional CMOS IC flow with the MEMS sensor on the same silicon die. This … [Read more...]
Industrial IoT (IIoT) – Where is Silicon Valley
Industrial Internet of Things (IIoT) has a market forecast approaching over one hundred billion, so it has everyone’s attention right now, except, it seems, Silicon Valley. Turning volumes of factory data into actionable information from the supply chain, to the floor, to operations, and up to … [Read more...]
Integrated Design Management for Collaborative IC Design
For IC design and verification teams, employing a data management tool is important for successful projects. Often, specific blocks are assigned to team members based on analog, digital, MEMS, RF expertise, across multiple geographies. Unstructured design files with multiple copies and versions, … [Read more...]
AI Accelerator Ecosystem: An Overview
As teams create custom machine learning acceleration blocks in C++, they often employ a High-Level Synthesis flow to quickly find power and performance solutions. But tools alone cannot jumpstart these projects. What they need is an ecosystem that provides support, ideas, and direction for their … [Read more...]
Machine Learning at the Edge: Using High-Level Synthesis to Optimize Power and Performance
Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for … [Read more...]
High-Level Synthesis for Autonomous Drive
Although RTL has traditionally been the starting point for digital design, it is becoming too expensive and time consuming. Algorithmic intensive hardware for AI in autonomous vehicles requires a new flow. Companies like BOSCH Visiontec, STMicroelectronics and Chips&Media have turned to a high-level … [Read more...]
Automated constraint checks enhance analog design reliability
Many layout-dependent and operational environment variation effects that reduce reliability are subtle and hard to predict. Analog designers use layout best practices to mitigate variation impact, but verification can be difficult, time-consuming, and prone to error. Automated layout checks can … [Read more...]