Design companies and foundries are constantly modifying their design implementation flows to deliver the best possible solution for their operational needs, and the best possible designs for the market. While the use of DFM tools can help shorten design iterations, they are typically not well … [Read more...]

Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. The conventional clock … [Read more...]

Emulation, combined with a rich assortment of virtualized versions of the many protocols that 5G will require, is the only practical way of ensuring that the first round of silicon built will be the production version, able to handle all of the functions and configurations that it might be faced … [Read more...]

Meeting the ISO 26262 requirements for high quality and long-term reliability mans implementing on-chip safety mechanisms with high defect coverage of IC logic. This paper describes Observation Scan Technology, a new new logic built-in-self-test (BIST) technology that improves logic BIST test … [Read more...]

Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for … [Read more...]

Increasing automotive design complexity demands a shift away from legacy automotive design flows that heavily rely on manual design work, data exchange, and requirements tracking. The industry demands generative design. In part one we examined these challenges and briefly described how a generative … [Read more...]

Most IC manufacturers use CMP modeling to detect potential hotspots as part of their DFM flow. However, building physics-based or compact models for FCVD and eHARP CMP processes has proven challenging, since these processes include several deposition and annealing steps to fill up trenches. … [Read more...]

Electrical rule checking (ERC) verifies the robustness of a schematic or layout design, ensuring that circuits will operate as designed and intended. ERC violations can result in reduced yield, or worse, potential circuit malfunction or electrical failure after product delivery. With its … [Read more...]

Artificial intelligence (AI) and machine learning (ML) are seeing growing adoption in a wide range of applications, due primarily to the improvement in algorithms, advancements in hardware design, and the increase in data volume created by digitization of information [1]. The integrated circuits … [Read more...]

Major advances in communications technology offer new opportunities and challenges for radio frequency (RF) design. 5G, the fifth generation of cellular technology, promises to deliver increased speed and improved flexibility of wireless services while reducing latency. The Internet of Things (IOT), … [Read more...]