Analog and Mixed/Signal IC designers face significant developmental challenges and unforgiving time-to-market expectations. This white paper explores how to solve those challenges.
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Siemens
Charting a path to operational excellence with smart manufacturing
Medical device manufacturers have traditionally used paper-based methods to guide and track the execution of manufacturing processes, including paper device history records (DHR). But industry leaders have made strides in adopting automated processes. However, now they are facing challenges in scaling these systems, especially across globally distributed production facilities and when contracting with manufacturing partners. Gathering, standardizing, and contextualizing real-time manufacturing data across all participants in the supply chain can enable automated validation of product equipment and processes.
Siemens, AMD, and Microsoft collaborate on EDA in the cloud
Moving some or all of your EDA computing to the cloud enables your company to reduce time-to-market and innovate faster by taking advantage of flexible cloud resources and economies of scale. Siemens EDA teamed up with AMD and Microsoft Azure to demonstrate how using the Calibre platform with cloud computing can dramatically reduce your design closure times. Using a production 7nm design, they achieved a 2.5X speed up in physical verification cycle time.
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New approaches to physical verification closure and cloud computing come to the rescue in the EUV era
Time-to-market is a critical commodity in the electronics industry, as is the cost-effective use of resources and engineer expertise. EDA suppliers constantly evaluate design information from both design houses and foundries to assess the impact of changing technology, and to develop and implement new functionality and tools that reduce time and resource impacts while improving accuracy and full coverage. Continuously developing smarter, more accurate, faster, and more efficient processes helps the industry improve both the bottom line and product quality, even in the face of increasing technological complexity.
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Calibre in the Cloud: Unlocking massive scaling and cost efficiencies
As companies look to leverage cloud capacity for faster turnaround times on advanced process node designs, they can be confident that running Calibre in the cloud provides the same sign-off verification results they know and trust, while enabling them to adjust their resource usage to best fit their business requirements and market demands.
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Critical area based test pattern optimization for high-quality test
Among the challenges for DFT engineers is how to set a target metric for ATPG and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected doesn’t consider the likelihood of one fault occurring compared to another. Tessent developed total critical area ATPG technology that enables the sorting and ordering of patterns based on their likelihood to detect defects. Users can create a pattern set for multiple fault models in one run, reducing the overall pattern size significantly.
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Embedded Analytics: A Platform Approach
Burgeoning complexity, both in systems-on-chip (SoCs) and in the embedded systems they enable, poses a challenge for the semiconductor industry. In this paper, we outline the multi-dimensional nature of this complexity and the costs and opportunities it generates. We demonstrate that the key to rising to this challenge is the ability to attain system-level visibility: both during the semiconductor development cycle, and subsequently after embedded systems are deployed in the field.
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Optimizing the integration of DFM and P&R
Design companies and foundries are constantly modifying their design implementation flows to deliver the best possible solution for their operational needs, and the best possible designs for the market. While the use of DFM tools can help shorten design iterations, they are typically not well integrated with P&R environments. To enable designers to transfer data from these tools to the P&R environment, database conversions are required. This paper introduces a solution for fast, accurate back-annotation of fill, via, and net objects to P&R applications.
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Systematic Methodology to Solve Reset Challenges in Automotive SoCs
Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. The conventional clock domain and CDC verification methodologies cannot identify such critical bugs. In this paper, we present a systematic methodology to identify and solve critical RDC bugs in automotive SoCs.
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5G verification is impossible without emulation
Emulation, combined with a rich assortment of virtualized versions of the many protocols that 5G will require, is the only practical way of ensuring that the first round of silicon built will be the production version, able to handle all of the functions and configurations that it might be faced with and having the tight performance characteristics needed for successful integration into a 5G system.
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