White Papers, Catalogs, Case Studies and Resources for Engineers and Professionals
This whitepaper outlines key architectural considerations required for the successful operation of smart devices within an IIoT infrastructure, with a focus on the software that runs on the device that allows for comprehensive and secure device management, telemetry, maintenance, and interoperability.
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5G SoC designs must support many use cases, custom configurations, and evolving standards. This means that a colossal amount of testing is required. Designers can no longer create fronthaul hardware based on a fixed network with connections and specifications that are locked down. 5G SoCs demand a new verification approach that meets the challenges of the exponential rise in required tests: a verification flow for pre- and post-silicon. The same testbenches and their tests and transactions need to run before and after the silicon is available. These testing suites need to be shared with partners developing other parts of the network in order to ensure interoperability. Learn how to create this new verification flow that combines emulation and X STEP, a platform that can generate, capture, and analyze bit-accurate fronthaul traffic.
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Electrical systems are constantly growing, whether in passenger cars, aircraft or heavy machinery. The growing size and complexity of these systems is driving up development costs and the likelihood of errors, potentially leading to even more cost or damaged brand reputation. Vehicle manufacturers can meet the demands of product complexity and quality while going to market faster than ever. Learn more in this paper.
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The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. Automotive ICs, once deployed for simple functions like controlling windows, are now performing complex functions related to advanced driver-assist systems (ADAS) and autonomous driving applications. The processing power required results in very large and complex ICs that use cutting-edge processes. Add in the need to meet the safety requirements of the ISO 26262 functional safety standard, and makers of automotive devices and systems have a new set of challenges. But functional safety is only half the story; these systems will only be safe if they are also secure from cyber threats like hacking.
The increase in complex functional safety and security content within these devices requires more control and monitoring. Upgrading from basic hardware controls to a scalable solution of an embedded CPU and software-controlled “safety island” is becoming extremely popular. This paper explores the concepts around a typical safety island implementation along with examples of how it can be used.
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Design and verification of electronic systems can be a challenging process, from the 100-plus page specification to the detailed measurements on the prototype in the lab. It’s even worse if your workflow is siloed, disconnected, and inefficient. If collaboration across your team is not optimized, it’s likely having a negative impact on your schedule, cost, and design quality.
Fortunately, there are measures an organization can take to alleviate these pain points. This new white paper walks through the six phases of the design lifecycle, using a high-speed DDR interface design as an example, and shows how you can improve process efficiency at every step.
Here are the six phases of the design lifecycle discussed in the white paper:
The paper explains why you should consider a deeper integration of your entire systems design flow with a seamless digital thread from concept through manufacture. That may sound daunting, but we break down how easily it can be achieved with the right tools.
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Aprisa overcomes advanced-node design complexities by taking into account the impact of detailed route information throughout the entire physical design flow. Aprisa’s unified data model (UDM) provides a single database for placement, optimization, routing and analysis. UDM is at the center of Aprisa’s innovative detailed-route-centric software architecture, making detailed route information available to any engine in Aprisa’s place and route flow. The result is faster time-to-closure with excellent quality-of-results.
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Accurate modeling of post-ECD surface topography variation is crucial for correct CMP simulation. Siemens and the American University of Armenia collaborated to investigate and evaluate the use of machine learning (ML) modeling techniques to predict these complicated topography variations. Using various ML methods to model post-ECD surface profiles and comparing the results enabled them to determine which architectures and models provided the best combination of running time and accuracy.
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Analog and Mixed/Signal IC designers face significant developmental challenges and unforgiving time-to-market expectations. This white paper explores how to solve those challenges.
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Medical device manufacturers have traditionally used paper-based methods to guide and track the execution of manufacturing processes, including paper device history records (DHR). But industry leaders have made strides in adopting automated processes. However, now they are facing challenges in scaling these systems, especially across globally distributed production facilities and when contracting with manufacturing partners. Gathering, standardizing, and contextualizing real-time manufacturing data across all participants in the supply chain can enable automated validation of product equipment and processes.
Moving some or all of your EDA computing to the cloud enables your company to reduce time-to-market and innovate faster by taking advantage of flexible cloud resources and economies of scale. Siemens EDA teamed up with AMD and Microsoft Azure to demonstrate how using the Calibre platform with cloud computing can dramatically reduce your design closure times. Using a production 7nm design, they achieved a 2.5X speed up in physical verification cycle time.
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