White Papers, Catalogs, Case Studies and Resources for Engineers and Professionals
2021 marks the 100th anniversary of Terumo, a global leader in medical technology based in Tokyo, Japan. Terumo Americas is its largest business, growing to huge product lines across four divisions over the last 50 years, including interventional systems, injection and infusion therapy devices and drug delivery devices.
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Siemens PAVE360 is a complete autonomous verification and validation environment modeled as a system that represents a twin image of the physical vehicle and its driving surroundings. Together with the EdgeLab.ai mixed-reality SW and HW 4/5G edge communication platform, Siemens PAVE360 powers the needs of OEMs and suppliers to explore, design, build and train/validate compute solutions critical to the future of connected and autonomous driving cars.
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5G SoC designs must support many use cases, custom configurations, and evolving standards. This means that a colossal amount of testing is required. Designers can no longer create fronthaul hardware based on a fixed network with connections and specifications that are locked down. 5G SoCs demand a new verification approach that meets the challenges of the exponential rise in required tests: a verification flow for pre- and post-silicon. The same testbenches and their tests and transactions need to run before and after the silicon is available. These testing suites need to be shared with partners developing other parts of the network in order to ensure interoperability. Learn how to create this new verification flow that combines emulation and X STEP, a platform that can generate, capture, and analyze bit-accurate fronthaul traffic.
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As the ultimate systems-of-systems, automated vehicles present an enormous verification task, requiring verification of complex sensing, computing, and actuating functions. This can be accomplished only by virtualizing the entire system — environment and vehicle — and through realistic scenario modeling, hardware emulation, and mechatronic verification. This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new cars on the road quickly, efficiently, and safely.
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Emulation in virtual mode simplifies debug, improves debug accuracy, creates new applications for emulation, and supports multiple concurrent users through remote access. This paper describes the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases. VirtuaLAB boosts productivity by delivering more testing in a shorter time frame, eliminating silicon respins, reducing risks, and improving ROI.
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CMP simulation is a valuable tool for determining the optimum CMP process to use during chip manufacturing. Large surface topography variations generated after ECD affect the post-CMP surface profile. In addition, weak long-range interactions of patterns on the design are inherent for post-ECD surface profiles, which means that the surface height above the given pattern is not defined solely by the pattern itself, but is affected by neighbor patterns. The ability to create an accurate post-ECD model is essential to successful CMP simulation.
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Ensuring your integrated circuit (IC) design has the ability to withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity in IC circuit design and verification. While automated flows for ESD verification are wellestablished for regular 2D ICs, 2.5D and 3D integration presents new challenges in both ESD design and verification. Although there are some design methodologies to help designers achieve effective ESD protection in 2.5D and 3D ICs, there has been, until now, a distinct lack of automated ESD verification solutions for these technologies. Let’s examine the verification challenges introduced by these integration technologies, and then walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.
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Modern electronic systems consist of increasingly complex combinations of hardware and software as a result of continued “digitalization.” Development of these two fundamental aspects of a system tend to happen over very different timescales, with hardware design starting as much as two years ahead of software.
But hardware verification and validation must include proof that the intended software works correctly on the hardware – a difficult task when software lags so far behind. A software-enabled verification and validation methodology, such as that delivered by Veloce HYCON, allows earlier hardware verification through early workload analysis, breaking the hardware dependency on system software.
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Automated post-processing DRC debugging flows enable designers to more quickly and accurately analyze and fix (or waive) a wide range of complex error conditions. By providing designers with more precise and detailed information about a wide variety of DRC/DFM errors, automated analysis and processing of errors, and visual displays of error distributions, the advanced post-processing functionality not only helps design teams move rapidly through debugging flows, saving valuable time and resources, but also improves design quality.
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Design complexities and time-to-market pressures compel companies to find innovative ways to leverage all available resources. “Not on premises” cloud compute environments provide a scalable and sustainable platform that can significantly improve runtimes in Calibre PERC flows and other demanding EDA compute tasks. Running Calibre PERC verification flows on cloud hardware resources to satisfy peak demand usage can increase productivity and expedite turnaround-times. Understanding the cost/ benefit relationship of cloud computing helps companies determine the optimal configuration that provides the greatest returns.
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