Siemens

Every IC designer strives to create a “clean,” or error-free, cell, block, chiplet, SoC, or 3DIC assembly before passing their work downstream for full signoff verification. However, waiting until … [Read more...] about Shift left to optimize IC design flow productivity and time to market

When manufacturing an integrated circuit, we have always made masks with Manhattan and 45-deg edges. Contact holes, for example, are designed square, even though the shape that is actually printed on … [Read more...] about Curves ahead! IC manufacturing prepares for curvilinear masks

As package designs evolve, so do verification requirements and challenges. Designers working on multi-die, multi-chiplet stacked configurations in 2.5/3D IC designs can use Calibre 3DSTACK physical … [Read more...] about Taking 2.5D/3DIC physical verification to the next level

The extensive use of MIM/MOM capacitors in analog/RF designs presents parasitic extraction challenges to designers. Understanding best practices and recommended tools for extracting the complex … [Read more...] about Parasitic extraction of MIM/MOM capacitor devices in analog/RF designs

Today’s technologies are combining processing power with sensors and analog circuitry at a scale that could only be dreamed of in the past. However, market success demands these combined systems also … [Read more...] about Scaling analog design power integrity analysis is critical to market success

Power integrity analysis evaluates circuits to determine if they will provide their designed/intended performance and reliability as implemented. Designers must be able to verify analog and digital … [Read more...] about Introducing mPower: Uncompromised power integrity for the whole design, at any scale

To fulfill the performance promise of 5G while ensuring 5G IC designs can be successfully manufactured in commercial quantities, designers of 5G chips and networks need accurate, automated parasitic … [Read more...] about Parasitic extraction challenges and solutions for 5G IC design

Moving some or all of your EDA computing to the cloud enables your company to reduce time-to-market and innovate faster by taking advantage of flexible cloud resources and economies of scale. Siemens … [Read more...] about Siemens, AMD, and Microsoft collaborate on EDA in the cloud

One of the biggest semiconductor engineering challenges today is delivering best-in-class devices while dealing with the technology scaling and cost limitations of monolithic IC design processes. To … [Read more...] about eBook: Deliver 3D IC innovations faster

When manufacturing an integrated circuit, we have always made masks with Manhattan and 45-deg edges. Contact holes, for example, are designed square, even though the shape that is actually printed on … [Read more...] about Curves ahead! IC manufacturing prepares for curvilinear masks