Companies worldwide trust the Catapult HLS Platform for designing and verifying machine learning accelerators and connecting them to systems. But, Mentor has taken a big step farther and offers an AI accelerator ecosystem that provides AI designers with an environment to jumpstart their projects. Based on years of working with designers, this ecosystem provides resources from IP libraries to full toolkits with real working designs. Learn all about this AI accelerator ecosystem by reading this whitepaper.
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Emulation, combined with a rich assortment of virtualized versions of the many protocols that 5G will require, is the only practical way of ensuring that the first round of silicon built will be the production version, able to handle all of the functions and configurations that it might be faced with and having the tight performance characteristics needed for successful integration into a 5G system.
While exotic technology for autonomous drive cars draw wonder all around the world, individual smart sensor systems with “simple” jobs to do are equally important. LiDAR sensors with specialized AI chips for object identification are fascinating. But “simple” smart sensor systems, like passenger airbag deployment systems, are also key to autonomous drive vehicles. A typical trait of a smart sensor system is that the sensing device is implemented using MEMS and the rest of the circuitry is an analog/mixed-signal (AMS) design implemented in a CMOS technology. Bridging those domains is not an easy task. Learn how these domains are united for automotive IC design in this paper.
Sensor-based designs, such as IoT systems, combine many design domains implemented on CMOS (Figure 1). These systems can be implemented on multiple dies and could employ multiple packages. To accommodate multiple sensor types, a traditional CMOS IC flow must be extended to include MEMS and photonics elements along with analog and digital elements. If the system communicates with the Cloud, an RF element is also necessary.
As the world continues to demand more performance, bandwidth, and capacity from smaller, lighter, and lowerpower products, so the increase in High Density Advance Packaging (HDAP) usage will grow.
PCI Express® (PCIe®) is a dominant technology for hardware applications requiring high-speed connectivity between networking, storage, FPGA, and GPGPU boards to servers and desktop systems. It is a robust technology that has evolved over decades to keep up with advancements in throughput and speed for I/O connectivity for computing requirements.
This brief provides a high level summary of advancements in Mentor’s AMS Verification solutions since we saw
Semiconductor content in today’s vehicles is growing rapidly and we are approaching the point where the value of the electronics is expected to exceed 50% of the total vehicle cost. A growing proportion of the modern-day automotive electronics are there to support new advanced driver-assistance systems (ADAS) like lane departure assist, collision avoidance, and other self-driving features. The demands of safety-critical ADAS systems introduce new challenges to semiconductor designers in meeting functional safety requirements defined by the ISO 26262 standard. 
Catapult® High-Level Synthesis (HLS) is hot in markets like Deep Learning/AI, Computer Vision, Communication (5G, IoT), and Video, just to name a few. Designing at the C++ or SystemC-level with a fast path to highest QofR (performance, area and power) for both FPGA and ASIC. Catapult’s ecosystem is more than just “C to RTL”, with HLSaware code and functional coverage similar to System Verilog, and formal equivalence checking, enabling competitive differentiation and accelerated time-to-market. Having a complete low-power methodology from block to SoC whether starting from C or RTL with PowerPro® is also critical in emerging ultra-low-power sensitive markets. This resource will help you find key sessions-panels at DAC from researchers, customers, and our expert technologists; and various resources detailing the recent innovations in HLS, Verification, and RTL Low-Power since DAC 2019.
UVM promised a perfect world where a common set of guidelines for testbenches and connected verification IP would make a compatible, simpler world. Just don’t look too closely at the standard. UVM carries baggage from previous standards such as OVM, VMM, eRM, AVM, and more. This paper describes situations where UVM provides multiple ways to solve a problem, and approaches outside of UVM, explains the issues with certain approaches, and recommends solutions, and describes the tradeoffs.