When designers move their untimed C++ design descriptions through a high-level synthesis (HLS) flow, they wonder if the generated, timed RTL is functionally equivalent to the original, high-level description. When they make refinements or optimize RTL for power, they naturally are concerned that … [Read more...]
A Case Study of RTL Power Optimization at NVIDIA
Graphic processing chips are known to push the technical limits of hardware design, semiconductor capability and power consumption. With every generation of chips, it becomes more important for engineers to: Minimize power consumption during peak processing loads Optimize power without … [Read more...]
What They Didn’t Teach you in Engineering School about Heat Transfer
Heat and its behavior are complex. Rules of thumb are often used to visualize the heat path for design or physical prototypes; but knowing how heat is traveling, at what speed and where it will go, is difficult. Read this newly refreshed white paper to learn how to understand heat flow and channel … [Read more...]
What They Didn’t Teach you in Engineering School about 3D Pressure Drop
Pressure loss is one of the greatest challenges faced by designers. After all, a pressure drop translates to a loss in energy which would have to be compensated by a higher energy demand. Therefore, it stands to reason that an optimized design resulting in the optimal pressure conditions, would … [Read more...]
Numerical Simulation of Transpupillary Thermotherapy for Intraocular Tumors
The use of computational methods in medicine, especially in practical medicine, is not widely spread. Primarily this is due to the difficulty of modeling specific medical procedures and their effects on the human organism, as well as the conservatism of the methods of treatment used for this. … [Read more...]
A Machine Learning Approach to CMP Modeling
As feature sizes decrease there is a growing need for chemical-mechanical polishing (CMP) modeling to better understand how the design layout impacts planarity. CMP modeling has proven to be very effective in simulating the profile when a process has a well-defined physics based model. In this IC … [Read more...]
Adopting an Interface DRC Checking Flow
Chip-level physical implementation teams must manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning, blocks placed in the chip-level floorplan may still be under development. Merging these incomplete blocks with the chip-level interconnect … [Read more...]
Integrating Pattern Matching with DFM Properties to Enhance and Optimize Layouts
In this IC design white paper we explore how the use of pattern matching has expanded into design for manufacturing (DFM) flows and integrates with different types of DFM properties (numeric, strings and vector properties). Leveraging these properties in pattern matching allows for several new … [Read more...]
Achieving Optimal Performance During Physical Verification
With increased complexity in design layout requirements at each new node, the compute burden placed on physical verification has grown exponentially. At the same time, designers are generally faced with less time to get their designs out the door. In this white paper, we detail the key steps you … [Read more...]
Color Optimization Considerations in Multi-Patterning
Decomposing multi-patterned design layers into colors has traditionally been an exercise in finding at least one DRC legal coloring solution. In this white paper we discuss how manufacturers at more advanced nodes are now finding significant yield and performance differences among DRC legal coloring … [Read more...]
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