In this paper you will learn through an example of another company to use AFS for circuit design signoff for a fractional-N PLL and a SerDes high-speed I/O circuit:
• AFS illustrates up to18X speedup when compared with traditional SPICE for PLL locking simulation.
• Runs a full circuit simulation of the SerDes circuit, including RX and TX PLL tuning voltages, lock signals with eye diagram measurement correlation.
• Improves productivity and performs large analog circuit signoff with nanometer SPICE accuracy with the ability to simulate jitter.