Chip-level physical implementation teams must manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning, blocks placed in the chip-level floorplan may still be under development. Merging these incomplete blocks with the chip-level interconnect for Calibre sign-off DRC produces a massive number of errors from the block core and along the block boundary at the chip-level interface. In our latest white paper, learn how you can achieve significant time savings by augmenting existing Calibre sign-off DRC flows with incremental interface DRC checking that excludes rules and data that cannot be reliably checked when blocks are incomplete.
Download this white paper from Mentor Graphics to learn more…