Major advances in communications technology offer new opportunities and challenges for radio frequency (RF) design. 5G, the fifth generation of cellular technology, promises to deliver increased speed … [Read more...] about Parasitic Extraction of MIM/MOM Capacitor Devices in Analog/RF Designs
Siemens
Improving Productivity With More Efficient LVS Debug
Layout vs. schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SOC) design cycle, but with today’s highly dense and hierarchical … [Read more...] about Improving Productivity With More Efficient LVS Debug
Fusing CMOS IC and MEMS Design for IoT Edge Devices
A new breed of designers are creating IoT edge devices that span across analog, digital, RF, and MEMS domains. They are tackling a challenge that once seemed impossible: combining the electronics of … [Read more...] about Fusing CMOS IC and MEMS Design for IoT Edge Devices
Industrial IoT (IIoT) – Where is Silicon Valley
Industrial Internet of Things (IIoT) has a market forecast approaching over one hundred billion, so it has everyone’s attention right now, except, it seems, Silicon Valley. Turning volumes of factory … [Read more...] about Industrial IoT (IIoT) – Where is Silicon Valley
Integrated Design Management for Collaborative IC Design
For IC design and verification teams, employing a data management tool is important for successful projects. Often, specific blocks are assigned to team members based on analog, digital, MEMS, RF … [Read more...] about Integrated Design Management for Collaborative IC Design
AI Accelerator Ecosystem: An Overview
As teams create custom machine learning acceleration blocks in C++, they often employ a High-Level Synthesis flow to quickly find power and performance solutions. But tools alone cannot jumpstart … [Read more...] about AI Accelerator Ecosystem: An Overview
Machine Learning at the Edge: Using High-Level Synthesis to Optimize Power and Performance
Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much … [Read more...] about Machine Learning at the Edge: Using High-Level Synthesis to Optimize Power and Performance
High-Level Synthesis for Autonomous Drive
Although RTL has traditionally been the starting point for digital design, it is becoming too expensive and time consuming. Algorithmic intensive hardware for AI in autonomous vehicles requires a new … [Read more...] about High-Level Synthesis for Autonomous Drive
Automated constraint checks enhance analog design reliability
Many layout-dependent and operational environment variation effects that reduce reliability are subtle and hard to predict. Analog designers use layout best practices to mitigate variation impact, but … [Read more...] about Automated constraint checks enhance analog design reliability
Configurable, easy-to-use, packaged reliability checks
Using a packaged checks flow lets designers quickly select, configure and run custom reliability checks and check combinations to help design companies achieve today’s demanding time-to-market … [Read more...] about Configurable, easy-to-use, packaged reliability checks